IEEE MWSCAS 2022 Keynote Speakers
Keynote 1: TBD
Vivek BhanSenior Vice President, Deputy General Manager of Automotive Solution Business Unit, Renesas Electronics Corp.
Mr. Vivek Bhan joined Dialog Semiconductor in 2013 and has served as Senior Vice President and General Manager of the Custom Mixed Signal Business (CMS) Group. In these roles, Mr. Bhan was responsible for leading global teams to diversify Dialog’s customer base and expand product offerings. He also oversaw product marketing and definition, system and application engineering, design engineering, software development, program management and also central engineering, which comprises process technology, CAD, Tools and IP.
Prior to joining Dialog, Mr. Bhan has previously held executive level and senior management positions at Fujitsu Semiconductor, Freescale and Motorola. In his previous capacities, Mr. Bhan led global product groups and teams providing solutions across multiple technologies including 2G/3G/4G, Zigbee, iDEN, GPS, BLE, Power, Battery, Display, Audio, RF and Digital SoCs.
Mr. Bhan holds a master’s degree in electrical engineering and an MBA from Arizona State University. He holds multiple patents and publications.
Keynote 2: Avatar and the future society
Hiroshi IshiguroProfessor, GraduateSchool of Engineering, Osaka University, Japan
Prof. Hiroshi Ishiguro has been doing research on teleoperated robots, for more than two decades. In his research, he developed a series of avatars, called Geminoids, which resemble himself. The study not only helps to understand humans and apply methods from engineering, cognitive science and neuroscience to various research topics, but also practically allows a person to be physically present and work in different places without travelling. The talk will introduce research and development of teleoperated androids, such as Geminoids, and discuss how humans and robots can coexist in future society.
Hiroshi Ishiguro received a Dr. Eng. Degree in systems engineering from the Osaka University, Japan in 1991. He is currently a Professor of Department of Systems Innovation in the Graduate School of Engineering Science at Osaka University (2009-) and Distinguished Professor of Osaka University (2017-). He is also visiting Director (2014-) (group leader: 2002-2013) of Hiroshi Ishiguro Laboratories at the Advanced Telecommunications Research Institute and an ATR fellow. His research interests include sensor networks, interactive robotics, and android science. He received the Osaka Cultural Award in 2011, the Prize for Science and Technology (Research Category) from the Minister of Education, Culture, Sports, Science and Technology (MEXT) in 2015, the Sheikh Mohammed Bin Rashid Al Maktoum Knowledge Award in Dubai in 2015, the Tateisi Prize in 2020, and the Reproducibility Award for GENEA Workshop in 2021.
Keynote 3: Big Data and Analytics: Challenges and Opportunities
Umeshwar DAYAL, Ph.D.,Senior Vice President, Big Data Lab, and Senior Fellow, Information Research at Hitachi America, Ltd and Corporate Chief Scientist, Hitachi, Ltd.
Nearly every sector of the economy is being transformed through digitalization driven by data. Through the proliferation of sensors, IoT (the Internet of Things), smart applications and devices, human-generated data, and access to open data, industrial operations are producing large volumes of rich data of different types. Big data and advanced analytics technologies enable the collection, integration, and processing of rich data from many sources at scale and speed. Typically, the objective has been to make industrial operations more efficient. With increasing social and environmental concerns stemming from climate change and depletion of natural resources, many industries are transitioning from the traditional linear economy to the circular economy in which products and materials are kept in use for as long as possible, reducing waste and pollution.
Opportunities arise to use big data and analytics technologies to make industrial operations more sustainable as well as more efficient. In this talk, we will discuss the challenges facing industry in digitalization and the transition to the circular economy, and we will show how big data, advanced analytics, and related digital technologies can address these challenges.
Dr. Umeshwar DAYAL, is currently a Corporate Chief Scientist of Hitachi. He joined Hitachi America, Ltd. in 2013 after serving as an HP Fellow in Intelligent Information Management and Director of the Information Analytics Lab at HP Labs. At the Hitachi America R&D Division, he led work on AI/big data analytics, and collaborative creation activities with customers as the Head of the Big Data Laboratory, and later as the GM of the Silicon Valley Research Center. Dayal was appointed to his current position in April 2020, after serving as the Head of the Global Center for Social Innovation responsible for the open co-innovation of novel digital solutions.
Dr. Dayal is an ACM Fellow, a recipient of the Edgar F. Codd Award from the ACM Special Interest Group on Management of Data (SIGMOD) for fundamental contributions to data management, and a Distinguished Alumnus Award from the Indian Institute of Science. He has over 250 research publications, holds over 60 patents, and has given over 40 keynote and invited lectures at international conferences and workshops. He has served on the Steering Committees of the IEEE International Conference on Data Engineering, and the Society of Industrial and Applied Mathematics Conference on Data Mining, and on the Board of Trustees of the VLDB Endowment. He has served as General Chair, Program Chair, and Program Committee member of numerous international conferences, and on the Editorial Board of several journals.
Keynote 4: A Data Linkage Platform for High Value-Added DX in Smart City Projects
Dr. Yuichi Nakamura,Vice President, NEC Corp., Japan
One major advantage of digital transformation (DX) is the ability to help create new services through the extraction of more detailed and essential information through the Integration across digitized data items of heterogeneous origins and of different kinds. Realizing this inevitably requires a mechanism for linking heterogeneous data items from different sources for efficient utilization. This talk introduces an open platform for linking data items of many different kinds and reports its usage in a couple of smart city projects.
Dr. Yuichi Nakamura received his B.E. in information engineering and M.E. in electrical engineering from the Tokyo Institute of Technology in 1986 and 1988, respectively. He received his PhD. from the Graduate School of Information, Production and Systems, Waseda University, in 2007. He joined NEC Corp. in 1988 and he led NEC’s research about embedded system design and quantum technologies as a general manager and a vice president of NEC research and development. Currently, he is an executive professional of NEC Corp. He is also a guest professor of National Institute of Informatics, Kyushu University, Waseda University and Tokyo University and an invited professor of Osaka University. He has more than 30 years of professional experience in electronic design automation, signal processing, super computer design, combinational optimization and quantum computing.
Dr. Yuichi Nakamura is an executive specialist of NEC. He contributed to manage and lead several innovative projects in signal processing and computing area. He has published more than 25 journal articles, 40 international conference papers and had many keynotes talks at major conferences, such as ISCAS2019, etc.
He is an advisory board member of Japanese government quantum innovation meeting, an evaluation committee of several Japanese government grant meetings. He is also a TP member of APSIPA SPS.
Keynote 5: Of Brains and Computerss
Jan M. RabaeyProfessor in the Graduate School, UC Berkeley, CTO STCO Division, IMEC, Belgium
The human brain – which we consider to be the prototypal biological computer –- in its current incarnation is the result of more than a billion years of evolution. Its main functions have always been to regulate the internal milieu and to help the organism/being o survive and reproduce. With growing complexity, the brain has adapted a number of design principles that serve to maximize its efficiency in performing a broad range of tasks. The physical computer, on the other hand, had only 200 years or so to evolve, and its perceived function was considerably different and far more constraint – that is to solve a set of mathematical functions. This however is rapidly changing. One may argue that the functions of brains and computers are converging. If so, the question arises if the underlaying design principles will converge or cross-breed as well, or will the different underlaying mechanisms (physics versus biology) lead to radically different solutions.
Jan is a Professor in the Graduate School in the EECS Department at the Universi ty of California at Berkeley, where he held of the Donald O. Pederson Distinguished Professorship for over 30 years before retiring. Before joining the faculty at UC Berkeley, he was a research manager at IMEC from 1985 until 1987. He is a founding director of the Berkeley Wireless Research Center (BWRC) and the Berkeley Ubiquitous SwarmLab, and has served as the Electrical Engineering Division Chair at Berkeley twice. In 2019, he also became the CTO of the System-Technology Co-Optimization (STCO) Division of IMEC, Belgium.
He has made major contributions to various fields including low power integrated circuits, advanced wireless systems, mobile devices, sensor networks, and ubiquitous computing. Some of the systems he helped envision include the infoPad (a forerunner of the iPad), PicoNets and PicoRadios, the Swarm, Brain-Machine interfaces and the Human Intranet. His current interests include the conception of the next-generation distributed systems, as well as the exploration of the interaction between the cyber and the biological worlds.
He is the recipient of major awards, amongst which the IEEE Mac Van Valkenburg Award, the European Design Automation Association (EDAA) Lifetime Achievement award, the Semiconductor Industry Association (SIA) University Researcher Award, and the SRC Aristotle Award. He is an IEEE Fellow, a member of the Royal Flemish Academy of Sciences and Arts of Belgium, and has received a number of honorary doctorates. He has been involved in a broad variety of start-up ventures.
Keynote 6: The Future of Hardware Technologies for Computing: N3XT 3D MOSAIC, Illusion Scaleup, Co-Design
Subhasish MitraProfessor of Dept. of EE and Dept. of CS, Stanford University, USA
The computation demands of 21st-century abundant-data workloads, such as AI /machine learning, far exceed the capabilities of today’s computing systems. For example, a Dream AI Chip would ideally co-locate all memory and compute on a single chip, quickly accessible at low energy. Such Dream Chips aren’t realizable today. Computing systems instead use large off-chip memory and spend enormous time and energy shuttling data back-and-forth. This memory wall gets worse with growing problem sizes, especially as conventional transistor miniaturization gets increasingly difficult.
The next leap in computing performance requires the next leap in integration. Just as integrated circuits brought together discrete components, this next level of integration must seamlessly fuse disparate parts of a system – e.g., compute, memory, inter-chip connections – synergistically for large energy and execution time benefits. This talk presents such transformative Nano Systems by exploiting the unique characteristics of emerging nanotechnologies and abundant-data workloads. We create new chip architectures through ultra-dense (e.g., monolithic) 3D integration of logic and memory – the N3XT 3D approach. Multiple N3XT 3D chips are integrated through a continuum of chip stacking/ interposer/wafer-level integration — the N3XT 3D MOSAIC. To scale with growing problem sizes, new Illusion systems orchestrate workload execution on N3XT 3D MOSAIC creating an illusion of a Dream Chip with near-Dream energy and throughput. Beyond existing cloud-based training, we demonstrate the first non-volatile chips for accurate edge AI training (and inference) through new incremental training algorithms that are aware of underlying non-volatile memory technology constraints.
Several hardware prototypes demonstrate the effectiveness of our approach. We target 1,000X system-level energy-delay-product benefits, especially for abundant-data workloads. Such large benefits enable coming generations of applications that push new frontiers, from deeply-embedded computing systems all the way to the cloud.
Dr. Subhasish Mitra is Professor of Electrical Engineering and of Computer Science at Stanford University. He directs the Stanford Robust Systems Group, leads the Computation Focus Area of the Stanford SystemX Alliance, and is a member of the Wu Tsai Neurosciences Institute. His research ranges across Robust Computing, Nano Systems, Electronic Design Automation (EDA), and Neurosciences. Results from his research group have influenced almost every contemporary electronic system, and have inspired significant government and research initiatives in multiple countries. He has held several international academic appointments - the Carnot Chair of Excellence in Nano Systems at CEA-LETI in France, Invited Professor at EPFL in Switzerland, and Visiting Professor at the University of Tokyo in Japan. Prof. Mitra also has consulted for major technology companies including Cisco, Google, Intel, Samsung, and Xilinx (now AMD). In the field of Robust Computing, he has created many key approaches for circuit failure prediction, on-line diagnostics, QED system validation, soft error resilience, and X-Compact test compression. Their adoption by industry is growing rapidly, in markets ranging from cloud computing to automotive systems. His X-Compact approach has proven essential for cost-effective manufacturing and high-quality testing of almost all 21st century systems, enabling billions of dollars in cost savings.
With his students and collaborators, he demonstrated the first carbon nanotube computer. They also demonstrated the first 3D NanoSystem with computation immersed in data storage. These received wide recognition: cover of NATURE, Research Highlight to the US Congress by the NSF, and highlight as "important scientific breakthrough" by global news organizations. Prof. Mitra's honors include the Harry H. Goode Memorial Award (by the IEEE Computer Society for outstanding contributions in the information processing field), Newton Technical Impact Award in EDA (test-of-time honor by ACM SIGDA and IEEE CEDA), the University Researcher Award (by the Semiconductor Industry Association and Semiconductor Research Corporation to recognize lifetime research contributions), the Intel Achievement Award (Intel’s highest honor), and the US Presidential Early Career Award. He and his students have published over 10 award-winning papers across 5 topic areas (technology, circuits, EDA, test, verification) at major venues including the Design Automation Conference, International Solid-State Circuits Conference, International Test Conference, Symposia on VLSI, and Formal Methods in Computer-Aided Design. He is an ACM Fellow and an IEEE Fellow.
Keynote 7: Image Sensor Technologies Extending the Sensing Capability
Dr. Yusuke OIKEDeputy Senior General Manager, SONY Semiconductor Solutions
The evolution of image sensors and the prospects utilizing advanced imaging technologies promise to improve our quality of life. The image sensor application is expanding to mobile devices, wearables, medical solutions, security networks, factory automation and autonomous driving while drastically accelerating the performance improvement and enhancing the functionality of imaging devices by stacking technologies. This talk introduces a broad overview of the key device technologies for image sensors, as well as circuit techniques, image signal processing and performance characteristics, that enable imaging applications in various fields. The next challenge of imaging system will be discussed for future society, where the imaging devices are integrating the extended sensing capabilities of spatial depth, temporal dynamics, invisible light, and inference.
Yusuke Oike has been involved in research and development of architectures, circuits, and devices for image sensors since joining Sony Corporation in 2005. He is now responsible for the development of CMOS image sensors as a deputy senior general manager of Sony Semiconductor Solutions and a distinguished engineer of Sony Group Corporation. Dr. Oike received the Ph.D. degree in electronic engineering from the University of Tokyo, Japan, in 2005. From 2010 to 2011, he was a visiting scholar at Stanford University, CA. His research interests include pixel architecture, mixed-signal circuit design, imaging device technologies, and image processing algorithms. He has been appointed as a distinguished engineer of Sony Group Corporation since 2019. He is also a board member of Sony Advanced Visual Sensing AG at Zurich, and a board member of International Image Sensor Society (IISS). He has served as the program chair and the symposium co-chair of VLSI Symposium 2021 and 2022, respectively, and also as TPC member of ISSCC from ’12 to ’16.