|August 7, 2022||Tutorial 1: Physical Design Optimization targeting Power Optimization||Ricardo Reis|
|August 7, 2022||Tutorial 2: Energy-Efficient and Low-Cost Hardware Security Primitives for Secure Ubiquitous Computing||Sachin Taneja|
|August 7, 2022||Tutorial 3: Thermal aware design of 3D Integrated Circuits using HotSpot 7.0||Mircea Stan
Mr. Jun-Han Han
All tutorials will be held on Sunday, August 7, 2022 a day prior to the formal start of the symposium on (August 9-11, 2022). All tutorials are free of charge for all MWSCAS 2022 participants.
TUTORIAL 1: Physical Design Optimization targeting Power Optimization
Ricardo ReisFull Professor, Instituto de Informática - Universidade Federal do Rio Grande do Sul, BRAZIL
The explosive growth of the number of transistors produced annually in the IOT world requires design methods capable of significantly reducing power consumption. Power optimization must be done at all levels of design abstraction, system, computer architecture till the physical design. This tutorial focuses on the optimization at physical design level. Nowadays, most circuits and systems are using more transistors than is needed. We will show some strategies to reduce the number of transistors and by consequence decrease power consumption, mainly static power. The reduction of the number of transistors also helps to improve routability and reliability. The reduction of the transistor count demands new tools to automatically generate the layout of any transistor network. EDA tools that can perform this task will be described.
Ricardo Reis received a Bachelor degree in Electrical Engineering from Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil, in 1978, and a Ph.D. degree in Microelectronics from the National Polytechnic Institute of Grenoble (INPG), France, in 1983. Doctor Honoris Causa by the University of Montpellier in 2016. He is a full professor at the Informatics Institute of Federal University of Rio Grande do Sul. His main research includes physical design automation, design methodologies, fault tolerant systems and microelectronics education. He has more than 700 publications including books, journals and conference proceedings. He was Vice-President of IFIP (International Federation for Information Processing), President of the Brazilian Computer Society (two terms) and Vice-President of the Brazilian Microelectronics Society. He is an active member of CASS and was Vice-President of CASS for two terms (2008/2011). He is the founder of the Rio Grande do Sul CAS Chapter, which got the World CASS Chapter of The Year Award 2011, 2012, and 2018, and R9 Chapter of The Year 2013, 2014, 2016, 2017 and 2020. He is a founder of several conferences like SBCCI and LASCAS, the CASS Flagship Conference in Region 9. He was the General or Program Chair of several conferences like IEEE ISVLSI, SBCCI, IFIP VLSI-SoC, ICECS, PATMOS. Ricardo was the Chair of the IFIP/IEEE VLSI-SoC Steering Committee, vice-chair of the IFIP WG10.5 and he is Chair of IFIP TC10. He also started with the EMicro, an annually microelectronics school in South Brazil. In 2002 he received the Researcher of the Year Award in the state of Rio Grande do Sul. He is a founding member of the SBC (Brazilian Computer Society), and a founding member of SBMicro (Brazilian Microelectronics Society). He was member of CASS DLP Program (2014/2015), and has given more than 70 invited talks in conferences. He is a Member of IEEE CASS BoG, IEEE CEDA BoG, Member of the IEEE IoT Initiative Activity Board and Chair of the IEEE CASS SiG on IoT. Ricardo received the IFIP Fellow Award, the 2015 IEEE CASS Meritorious Service Award, and the ACM/ISPD 2022 Lifetime Achievement Award.
TUTORIAL 2: Energy-Efficient and Low-Cost Hardware Security Primitives for Secure Ubiquitous Computing
Sachin TanejaPh.D., Research Scientist, Intel Labs, Ph.D., National University of Singapore
Security of ubiquitous connected systems (e.g., IoT nodes) has gained more importance due to the growing cost of security breaches. The security of these devices can be easily compromised with malicious physical access due to in-field operation and the recent affordability of physical attacks.
Design of the secure system on chip (SoC) requires energy-efficient and low-cost hardware security primitives (e.g., physically unclonable functions or PUFs, true random number generators or TRNGs, cryptographic cores) to implement hardware root-of-trust and execute cryptographic security protocols. Different design challenges for hardware security primitives are low energy efficiency, high silicon footprint, excessive design margin, robust operation across operating conditions and design methodology.
This tutorial will build up the basic requirements for the design of secure SoC. Different hardware security primitives are then discussed starting from the fundamentals, related design procedures, trade-offs to state-of-the-art implementations. Also, challenges and potential directions will be discussed for future research.
Motivation and Focus
Security of ubiquitous connected systems (e.g., IoT nodes) has gained more importance than the traditional system design PPA (i.e., power, performance and area) in the recent decade. Securing connected systems down to the hardware level is one of the important tasks with requirements of dedicated security subsystems in current SoC designs (e.g., NXP LPC55S6x MCU with security subsystem ), confirming the timely delivery of this topic essential for the innovative and novel design of next-generation secure SoC.
This tutorial synchronizes and aligns well with the ongoing theme of hardware security as an emerging threat to the design of integrated circuits (IC) in the last two decades and will result in the attraction of a wider audience to learn this important topic.
The tutorial will equip the audience with the design fundamentals, state-of-the-art design implementations and future directions for hardware security primitives. Also, this will serve as a small step towards training the next generation engineers, innovators and IC designers responsible for the design of secure SoC highly required for a highly connected but highly secure world.
Following will be the tentative syllabus of the proposed tutorial with covered topics showing relative contribution in brackets. Introduction of hardware security till physically unclonable functions (PUFs) will be covered in the first half-session covering approximately 50% of the tutorial while the second half-session of the tutorial will discuss from true random number generators (TRNGs) to future directions.
- Overview and Fundamental of Hardware Security Primitives (15%)
Overview of hardware security will set the stage for the main topic of hardware security primitives design. Energy-efficient and cost-constrained design of the SoC for secure integrated systems require efficient hardware security primitives to implement hardware root-of-trust and execute a variety of different security tasks (e.g., authentication, attestation, data exchange etc.) A brief overview of the fundamentals of different hardware security primitives will be presented.
- Design Challenges (10%)
Different design challenges encountered for the widespread adoption are low energy efficiency, design margining and robust operation across varying operating conditions -. This results in reduced battery life and fixed worst-case design, low area efficiency increasing the design cost, and complex testing (e.g., sweep and calibration) resulting in higher testing cost. Often, physical design aspects and methodologies are ignored, making them prone to physical attacks on data movement between blocks (i.e., data locality).
- PUF and TRNG (40%)
Physically unclonable functions (PUFs) provide a volatile way of static entropy generation from IC manufacturing for secure keys and authentication. True random number generators (TRNGs) are commonly used to generate time-varying random output (i.e., dynamic entropy) from random physical phenomena. Basics fundamentals for PUFs and TRNGs will be presented to address the wider experience range of the audience followed by different metrics and design procedures. A review of state-of-the-art designs addressing different design challenges will be presented next with comparisons. This will equip the audience with the latest developments from researchers around the world including the speaker -.
- Unified Designs (15%)
The emerging paradigm of unified designs combining different functions will be discussed to motivate the audience about the system-level holistic approach from the security perspective. Different state-of-the-art works will then be presented as case studies including the speaker research contributions -.
- Private-Key Cryptographic Accelerators (5%)
Hardware accelerators for private-key cryptography enable energy-efficient bulk data transfer. Private-key-cryptographic accelerators basics followed by state-of-the-art will be presented in brief including the speaker contribution .
- Future Directions (15%)
Future challenges and directions will be finally presented to motivate future researchers.
Sachin Taneja received the B.Tech. degree in electronics and communication engineering from Guru Gobind Singh Indraprastha University, New Delhi, India, in 2013, and the Ph.D. degree in electrical and computer engineering from the National University of Singapore, Singapore, in 2021. He is currently a Research Scientist at Intel Labs, Hillsboro, OR, USA. He was with Synopsys Inc., India, as Research and Development Engineer from 2013 to 2016 where he was involved in designing high-speed circuits and architectures for on-chip embedded memories. His research interests include the design of hardware security primitives and in-memory compute accelerators.
He was a recipient of the IEEE Solid-State Circuits Society (SSCS) Predoctoral Achievement Award in 2020-2021. He serves as an Associate Editor for IEEE Transactions on Circuits and Systems II and a Technical Program Committee member for various IEEE conferences. He also serves as a reviewer for the IEEE Journal of Solid-State Circuits, IEEE Transactions on Circuits and Systems I, IEEE Transactions on Very Large-Scale Integration Systems, IEEE Transactions on Circuits and Systems II, IEEE Internet of Things Journal and various IEEE conferences.
TUTORIAL 3: Thermal aware design of 3D Integrated Circuits using HotSpot 7.0
Mircea StanVirginia Microelectronics Consortium (VMEC) Professor
Jun-Han HanDept. Electrical and Computer Engineering, University of Virginia.
3D Integrated Circuits (3D IC) offer many advantages over their 2D counterparts, such as increased bandwidth and energy efficiency, which has led to the popularity of commercial products such as HBM and HMC. However, they also have well-known thermal challenges that come from dimension mismatch between volumetric heat generation and surficial cooling. 3D stacked ICs generate heat in each layer, increasing heat flux generation, but still have the same surface area as 2D ICs for surface cooling. The lack of cooling capacity limits power consumption in the 3D-stacked ICs. Previous studies have shown that conventional air-cooling methods for 2D-ICs have been unable to solve the thermal issues in 3D-stacked memories operating in-memory computing. Microfluidic cooling is a promising solution to these thermal challenges, but its associated design space is large enough and complex enough that we need a design space exploration tool. Consequently, an extensive understanding of the thermal behavior of the 3D-IC is required.
To create a tool that allows for thorough early-stage design space exploration, we start with HotSpot 6.0, an existing thermal simulator capable of simulating 3D IC and extend its thermal model to support microfluidic cooling. HotSpot requires very little information (such as a 3D IC’s dimensions and power dissipation values) to perform a simulation, making it suitable for the pre-RTL design space exploration that we want to achieve. HotSpot 6.0 models a 3D IC by discretizing it into an array of 3D cells, then modeling each cell as one node in a thermal circuit. This circuit can then be analyzed using well-established circuit analysis techniques to find the temperatures at each node, which correspond to the temperatures within each cell throughout the 3D IC. To support microfluidic cooling, we extend the thermal model to also support modeling heat transfer due to convection. We model each microfluidic cooling layer using a pressure circuit by taking advantage of the similarities between Ohm’s Law and the Hagen-Poiseuille Law. In the pressure circuit, voltage is analogous to pressure, current flow is analogous to fluid flow, and electrical resistance is equivalent to hydraulic resistance. Convective heat transfer from a solid cell to an adjacent fluid cell is modeled using a thermal resistance between the two cells.
We recently released a new version of HotSpot to support flexible modeling and simulation of microfluidic cooling designs. We believe this tool will enable research into novel microfluidic cooling techniques, ultimately resulting in higher performance 3D IC with reduced thermal constraints. This tutorial has four main chapters. The first chapter introduces thermal issues of 3D-IC and useful background information. We will investigate thermal simulation studies and newly released HotSpot 7.0 in the second and third chapters. The last chapter will talk about the thermal management of processing-in-3D-stacked-memory. The fast and accurate pre-RTL thermal simulator can be helpful to chip designers who are concerned with the high-power consumption or operating temperature of their work.
Mircea R. Stan is teaching and doing research in the areas of high-performance low-power VLSI, Processing in Memory, temperature-aware circuits and architecture, Cyber-Physical Systems, spintronics, and nanoelectronics. He leads the High-Performance Low-Power (HPLP) lab and is an associate director of the Center for Automata Processing (CAP). He presented the topic of PIM in the IEDM 2018 short course: “It’s All About Memory, Not Logic!!!”. Prof. Stan received the Ph.D. (1996) and the M.S. (1994) degrees from UMass Amherst and the Diploma (1984) from the Politehnica University in Bucharest, Romania. Since 1996 he has been with the ECE Department at UVa, where he is now the Virginia Microelectronics Consortium (VMEC) Professor. He was a co-author on best paper awards at ASILOMAR19, LASCAS19, SELSE17, ISQED08, GLSVLSI06, ISCA03 and SHAMAN02 and IEEE Micro Top Picks in 2008 and 2003. He gave keynotes at DCAS18, SOCC16, CogArch16, WoNDP15, iNIS15 and CNNA14. He is Associate Editor-in-Chief for the IEEE TVLSI, Senior Editor for the IEEE TNano, AE for IEEE Design & Test, and was an AE for the IEEE TNano in 2012-2014, IEEE TCAS I in 2004-2008 and for the IEEE TVLSI in 2001-2003. Prof. Stan is a fellow of the IEEE, a member of ACM, and of Eta Kappa Nu, Phi Kappa Phi and Sigma Xi. His h-index is 55 and his i10-index is 150.
Jun-Han Han is a Ph.D. candidate at the Electrical engineering department of the University of Virginia. Han received his BS and MS in electronic engineering from Hanyang University, Seoul, Korea, in 2007 and 2009, respectively. After graduating, he joined a Korean government research institute, ETRI, where he worked on OLED displays and flexible electronics. He moved to the University of Virginia, VA, USA, in 2017 and start his research on in-memory computing devices. He was a co-author on best paper awards at UD-DAC2021, JID2019, IMID2019, IMID2017, and IWFPE 2010. Jun-Han’s h-index is 18 and his i10-index is 31.